1. Field of the Invention
The present invention relates to a library group structured of logic gates and function blocks and a semiconductor integrated circuit structured of the library group. In particular, the present invention relates to a library group structured of logic gates and function blocks that satisfy both requirements of high speed operation and low power consumption and a semiconductor integrated circuit structured of the library group.
2. Description of the Related Art
A logic circuit for use in combination with a semiconductor integrated circuit (hereinafter referred to as an LSI; a large scale integrated circuit) is structured of logic gates (such as inverter, NAND gates, and OR gates) and/or function blocks (such as flip-flop circuits structured of several gates to several dozens of gates) which themselves have logically coherence. These logic gates and/or function blocks are designed before an LSI is individually designed. The designed logic blocks and function blocks are provided as a library group of a database. Thus, to design a logic LSI, logic gates and function blocks provided as a library group are placed on a chip and mutually connected.
Usually, a logic circuit of an LSI is formed on an array of basic transistors that have the same size. Examples of arrays are gate arrays and embedded arrays. For example, in a CMOS LSI, a basic cell is structured by plural P channel type basic transistors and plural N channel type basic transistors. The basic cells are generally arranged in an array shape.
The logic gates and function blocks should have a load capacitance driving capability along with a logic function. The load capacitance is composed of a next stage input capacitance and a wiring capacitance. The load capacitance is quantitatively defined with the number of gates connected to output (referred to as the number of fan-outs) and the wiring length between the output and the next stage. The number of fan-outs and the wiring length largely depend on each gate and each block. If we try to design a load capacitance driving capability individually and optimally, a precise wiring capacitance and a very long designing time may be required. However, a precise wiring capacitance may not be obtained until the layout design has been completed. Therefore, it is not realistic that the load capacitance driving capability is individually and optimally designed.
To solve this problem, assuming a standard logic gate and a standard load condition, the size of a basic transistor with a desired delay time is predetermined. As a standard logic gate, a three-input NAND gate is considered. In addition, as a standard load condition, the number of fan-outs is three and the wiring length is about 2 mm is normally considered. Thus, in a CMOS LSI, the channel width of a basic transistor is designated 10 to 20 .mu.m.
For a load larger than the standard load condition, a logic gate with a large load driving capability or a special driver circuit is provided. For example, for a simple logic gate or the like, a structure of which plural same gates are connected in parallel is conventionally provided. This structure is referred to as a power gate.
In a library group structured of such logic gates and function blocks and an LSI structured of the library group, speed and power consumption performance are not optimized. In other words, it is difficult to satisfy both the requirements of high speed and low power consumption.
In the case of, for example, a CMOS circuit, the load driving capability depends on the logic structure and the ratio between the channel width and the channel length of a MOSFET. For example, in the case of a three-input NAND gate, three N channel MOSFETs are connected in series. In the discharge state, the load driving capability of the three-input NAND gate is decreased to one third of that of an inverter gate. To drive the standard load at a high speed in such a situation, the channel width of a basic transistor is designed as large as 10 to 20 .mu.m. However, when the wiring length is short and the load of the fan-outs is dominant, the delay time does not depend on the channel width of the MOSFET, and the power is wasteful corresponding to the size of the basic transistor. In conventional logic circuits, half of logic gates and function blocks represent such a tendency. In particular, most of them in the data-pass portion almost represent such a tendency.
On the other hand, when the size of the basic transistors is simply reduced, although such a loss of the power can be reduced, if the fan-out load is not dominant, the operation speed deteriorates. In the case of a power gate, which is used to improve the load driving capability, since the area becomes twice or more, when the logic function becomes complicated, the areal efficiency remarkably deteriorates.
To solve such a problem, a structure that independently provides a portion that performs a logic function and a portion that performs a load driving function has been proposed in Japanese Patent Laid-Open Publication No. 63-43345 (this is referred to as the related art reference 1). For example, as shown in FIGS. 12(a) and 12(b), a two-input AND gate is divided into a two-input NAND gate and an inverter circuit. The former has a logic function, while the latter has a load driving function. They are applied for a standard cell as shown in FIG. 12(c). After the layout design has been completed, the size of an output transistor that structures the inverter circuit is optimally designated corresponding to the load. When this method is applied for a gate array or an embedded array, if necessary, plural transistors are connected in parallel so that the size of an output transistor that structures an inverter circuit is optimally designated corresponding to the load.
A structure of which at least an output block is connected in parallel so that a predetermined fan-out characteristic can be obtained has been proposed in Japanese Patent Laid-Open Publication No. 63-46748 (this is referred to as the related art reference 2). For example, as shown in FIG. 13, in a logic circuit structured of three two-input NAND gates, a NAND gate at the last stage is connected in parallel corresponding to the load.
In the related art reference 1, the portion that performs the logic function can be structured of small transistors. In the related art reference 2, the portion of function blocks other than an output block can be structured of small transistors. Thus, the power consumption can be reduced without a decrease of the operation speed.
However, in the conventional library group structured of logic gates and function blocks and an LSI structured of the library group, when a gate array and an embedded array structured of basic transistors that have the same size are especially used, the designing time and areal efficiency are very wasteful.
Unless the layout design of an LSI has been completed, the load thereof cannot be precisely obtained. Thus, there may be a large difference between the load that has been initially estimated and the real load of the LSI. When the real load is greater than the initially estimated load, the load driving capability should be increased so as to prevent the operating speed from decreasing. On the other hand, when the real load is smaller than the initially estimated load, the load driving capability should be decreased so as to reduce the power consumption. In other words, after the placement and wiring have been designed, the load should be precisely estimated corresponding to the real designed result. When the real load is larger than the initially estimated load, the load driving capability should be increased so as to prevent the operating speed from decreasing. When the real load is smaller than the initially estimated load, the load driving capability should be decreased so as to reduce the power consumption without a sacrifice of the operating speed.
To do that, a library group structured of plural logic gates and function blocks that have the same logic function and that have different load driving capability should be provided so that proper logic gates and proper function blocks can be replaced. However, since the sizes and input/output terminal positions of the conventional library group differ from each other, the placement and wiring design should be performed again from the beginning. Thus, a very long designing time is required. In occasion, a rework may result in another rework, and after redesign of the placement and wiring design, may be performed for other positions. In addition, this rework does not guaranteed that the design is completed.
An increase of the load driving capability in the related art reference 3 is equivalent to the case that an output block is structured of a power gate. Thus, when the logic function of the output block is complicated, the areal efficiency remarkably deteriorates.